DATC RDF-2021: Design Flow and Beyond Jianli Chen1, Iris Hui-Ru

DATC RDF-2021: Design Flow and Beyond Jianli Chen1, Iris Hui-Ru Jiang2, Jinwook Jung3, Andrew B. Kahng4, Seungwon Kim4, Victor N. Kravets3, Yih-Lang Li5, Ravi Varadarajan4, and Mingyu Woo4 1 2 3 4 GitHub GitHub Link: Link: https://github.com/ieee-ceda-datc https://github.com/ieee-ceda-datc 5

Outline Introduction - Design Automation Technical Committee (DATC) - DATC Robust Design Flow (RDF) DATC RDF-2021 Flow and Updates - DATC RDF-2021 Flow - DATC RDF-2021 Updates New Directions - METRICS2.1 - Flow parameter auto-tuning - Calibration repository Summary 2

Design Automation Technical Committee (DATC) A technical committee of IEEE Council on EDA (CEDA) - Provide a forum for discussing strategies and issues in design automation Task: DATC Robust Design Flow (RDF) - Academic reference RTL-to-GDS design flow - Free for academic and noncommercial research - Supports complete RTL-to-GDS path for any use based on OpenROAD tool chains Committee Jinwook Jung Andrew B. Kahng Victor N. Kravets Jianli Chen Yih-Lang Li Iris Hui-Ru Jiang Affiliation IBM Research, USA UC San Diego, USA IBM Research, USA Fudan Univ., China National Yang Ming Chiao Tung Univ., Taiwan National Taiwan Univ., Taiwan Role Chair / Integration Vice chair / Flow Logic synthesis Placement Routing Previous chair 3

DATC Robust Design Flow (RDF) Academic reference design flow - Initiated 2016; latest release 2021 - Synthesis to detailed routing flow built upon outstanding contest-winning academic tools - Also supports complete RTL-to-GDS flow with OpenROAD tool chains RDF Goal: 1. Preserve and integrate leading research codes, including contest outcomes 2. Trigger design flow and cross-stage optimization research via various EDA tools developed from academia GitHub repository https://github.com/ieee-ceda-datc/datc-rdf Component Tool RTL generator Chisel/FIRRTL RTL obfuscation ASSURE Logic synthesis Yosys ABC DFT insertion Fault Floorplanning TritonFP Global placement RePlAce, FZUplace, NTUPlace3, ComPLx, Eh?Placer, FastPlace3-GP Detailed placement OpenDP, MCHL, FastPlace3-DP Flip-flop clustering Mean-shift, FlopTray Clock tree synthesis TritonCTS Global routing FastRoute4-lefdef, NCTUgr, CUGR Detailed routing TritonRoute, NCTUdr, DrCU Layout finishing KLayout, Magic Gate sizing Resizer, TritonSizer Parasitic extraction OpenRCX STA OpenSTA, iTimerC Database OpenDB Libraries/PDK NanGate45, SKY130, ASAP7, NCTUcell Benchmark conversion RosettaStone 4

Outline Introduction - Design Automation Technical Committee (DATC) - DATC Robust Design Flow (RDF) DATC RDF-2021 Flow and Updates - DATC RDF-2021 Flow - DATC RDF-2021 Updates New Directions - METRICS2.1 - Flow parameter AutoTuner - Calibration repository Summary 5

DATC RDF-2021 Flow Starts from pure Verilog or Chisel-generated Verilog (optionally obfuscated) Logic synthesis followed by DFT insertion P&R done with OpenROAD integrated app or point tool-based RDF flow Verilog Scala Netlist, SDC, parms Chisel/FIRRTL Chisel/FIRRTL Locking key RTL RTL Obfuscation Obfuscation Locked RTL SDC P&R P&R Flow Flow Logic Logic Synthesis Synthesis OpenROAD Integrated App RDF Point Tool Based Flow DFT DFT Insertion Insertion Routed design 6

DATC RDF-2021 Updates 1. 2. 3. 4. 5. Chisel and hardware generator designs support RTL obfuscation with ASSURE ABC synthesis script updates DFT support with Fault Robust Bookshelf-LEF/DEF conversion with RosettaStone 7

Chisel and Hardware Generator Designs Chisel: Constructing Hardware In a Scala Embedded Language - Provides special classes, predefined objects, language convention for hardware design Easy to implement highly-parameterized, abstract hardware generators Substantial interest from computer architecture researchers Link: https://www.chisel-lang.org Example open-source Chisel designs - Rocket Chip Generator Gemmini deep learning accelerator RISC-V BOOM Hwacha vector processor Davis In-Order (DINO) CPU models import import chisel3. chisel3. class class Filter Filter (bitWidth: (bitWidth: Int) Int) extends extends Module Module {{ val val io io IO(new IO(new Bundle Bundle {{ val val in in Input(UInt(bitWidth.W)) Input(UInt(bitWidth.W)) val val out out Output(UInt(bitWidth.W)) Output(UInt(bitWidth.W)) }) }) val val z1 z1 RegNext(io.in) RegNext(io.in) val val z2 z2 RegNext(z1) RegNext(z1) io.out io.out : : (io.in*1.U) (io.in*1.U) (z1*1.U) (z1*1.U) (z2*1.U) (z2*1.U) }} // // Parameterized Parameterized instantiation instantiation val val movingSum3Filter movingSum3Filter Module(new Module(new Filter(8)) Filter(8)) 8

RTL Obfuscation with ASSURE ASSURE: RTL obfuscation framework assuming netlist-only threat model 3 obfuscation techniques: - Constant: substitute constants in RTL with secret locking key - Operation: adds redundant operators alongside original operators in RTL - Branch: obfuscates branch conditions in RTL [Pilato et al., IEEE TVLSI 2021] 9

ABC Synthesis Script Updates Latest ABC updates incorporated in RDF-2021 - Tight integration of SAT solver with internal design representation - Improved scalability and new options to improve technology mapping quality - Example: verification task runtime improvement (10x faster than previous version) LazyMan synthesis scripts - Reuse logic rewriting choices empirically discovered in earilier runs - Included in RDF-2021 logic synthesis script abc abc 01 01 &cec &cec -x -x cnn.170.aig cnn.170.aig cnn.187.aig cnn.187.aig Networks Networks are are equivalent. equivalent. Time Time 1238.07 1238.07 sec sec abc abc 02 02 &cec &cec cnn.170.aig cnn.170.aig cnn.187.aig cnn.187.aig Networks Networks are are equivalent. equivalent. Time Time 12058.28 12058.28 sec sec Combinational equivalence checking runtime comparison 10

DFT Support with Fault Fault: open-source DFT infrastructure including scan insertion and ATPG - Supports scan chain insertion as well as ATPG flows - Scan chain insertion: add test signals, scan chains, and JTAG interface - ATPG: generate compressed test vectors Scan insertion Netlist Netlist with scan chains Chain Tap Netlist with tap ports ATPG Cut Comb-only netlist PGen Test vectors Compact Compacted test vectors 11

Robust Bookshelf-LEF/DEF Conversion with RosettaStone RosettaStone: robust benchmark converter powered by OpenDB - Creates OpenDB databases from bookshelf and PDK information - Missing information (e.g., cell types) are populated based on target PDK - Existing macro blocks are properly scaled based on placement site definitions - Also capable of converting LEF/DEF into bookshelf through OpenDB adaptec1 bigblue1 newblue2 superblue18 12

Outline Introduction - Design Automation Technical Committee (DATC) - DATC Robust Design Flow (RDF) DATC RDF-2021 Flow and Updates - DATC RDF-2021 Flow - DATC RDF-2021 Updates New Directions - METRICS2.1 - Flow parameter AutoTuner - Calibration repository Summary 13

METRICS2.1 – Previous Works on “METRICS” METRICS 1.0 [Fenstermaker et al., DAC’99; Kahng et al., ISQED’01] - “METRICS encompasses the instrumentation of design tools and design processes, the collection of design artifact and design process data, and the prediction of future results and data based on current information.” – Source: http://vlsicad.ucsd.edu/GSRC/metrics METRICS 2.0 [Hashemi et al., WOSET’18] - Revisit METRICS1.0 and propose updated architecture for collection and sharing of data for machine learning applications METRICS2.1 - Extension to METRICS 2.0, formalizing METRICS syntax and realization - Provides OpenROAD-based realization as well as public metrics data repositories 14

METRICS2.1 Link: Link: https://github.com/ieee-ceda-datc/datc-rdf-Metrics4ML https://github.com/ieee-ceda-datc/datc-rdf-Metrics4ML Consolidated design and flow metrics collected from tool logs DATC’s GitHub repository provides: - Metrics dataset collection obtained from OpenROAD flow with public enablement - Sample Jupyter notebooks on datasets to provide example ML applications Tool A Synthesis Tool B Floorplan Tool C Placement Tool D CTS Tool E Routing Tool F Verification Log Big Data Collection METRICS2.1 ML Applications Hierarchical JSON Object Flow autotuning SPECIAL SPECIAL SESSION SESSION 7C-1 7C-1 “METRICS2.1 “METRICS2.1 and and Flow Flow Tuning Tuning in in the the IEEE IEEE CEDA CEDA Robust Robust Design Design Flow Flow and and OpenROAD” OpenROAD” 15

Flow Parameter AutoTuner Link: Link: https://github.com/ieee-ceda-datc/datc-rdf-flow-tuner https://github.com/ieee-ceda-datc/datc-rdf-flow-tuner Smart flow parameter tuner of RTL-to-GDS flow utilizing UC Berkeley Tune - Flexible interface to define target parameters and objective function Design flow agnostic; support both academic and commercial flows Multiple search algorithm, e.g., PBT, HyperOpt, Optuna, etc. Parallel flow execution for efficient tuning Option 1 Best known parameter set Parameter config parameter name, range, step, type Search algorithm (switchable) Objective function Tuning options #trials, #cores, etc. Flow AutoTuner RTL-to-GDS flows are automatically executed in parallel Option 2 No prior knowledge Parallel execution Select parameter set based on config / results Create RTL-to-GDS flow with selected parameter set Execute RTL-to-GDS flow Collect METRICS2.1 json Evaluate reward function 16

Flow Parameter AutoTuner – Demonstration Design/tech: ibex/SkyWater 130nm HD Design flow: OpenROAD Flow parameter: 9 OpenROAD tool parameters Objective function: weighted sum of wirelength, delay, and power Search algorithm: HyperOpt 17

Flow Parameter AutoTuner – Demonstration Parameter tuning results (visualized by TensorBoard) Dots trials Objective Wall time Default Default flow flow score score 1,174,346 1,174,346 Best Best Score Score 855,373 855,373 (less (less isis better) better) Wirelength 1003801um 843258um (-16%) Critical path delay 20.935ns 16.185 ns (-23%) Power 0.024 W 0.0133 W (-45%) SPECIAL SPECIAL SESSION SESSION 7C-1 7C-1 “METRICS2.1 “METRICS2.1 and and Flow Flow Tuning Tuning in in the the IEEE IEEE CEDA CEDA Robust Robust Design Design Flow Flow and and OpenROAD” OpenROAD” 18

Calibration Repository Link: Link: https://github.com/ieee-ceda-datc/datc-rdf-calibrations https://github.com/ieee-ceda-datc/datc-rdf-calibrations To support academic research on analyses and verifications (started in 2020) Provides reference analysis data for STA, RCX, and IR drop obtained from DRV-free routed testcases in open enablements Updates in 2021 - Expanded dataset: {NanGate45, SKY130} X {GCD, AES, JPEG, IBEX} - New scripts to introduce noise in calibration data to enable obfuscations NanGate45-AES NanGate45-JPEG SKY130-AES SKY130-JPEG 19

Outline Introduction - Design Automation Technical Committee (DATC) - DATC Robust Design Flow (RDF) DATC RDF-2021 Flow and Updates - DATC RDF-2021 Flow - DATC RDF-2021 Updates New Directions - METRICS2.1 - Flow parameter AutoTuner - Calibration repository Summary 20

Summary DATC RDF 2021 Updates 1. 2. 3. 4. 5. Chisel and hardware generator support RTL obfuscation using ASSURE ABC synthesis script updates DFT support with Fault toolchain Robust benchmark conversion with RosettaStone New initiatives 1. METRICS2.1 for common metrics standardization for AI/ML applications 2. Flow autotuning framework supporting various design flows and search algorithms 3. Expanded calibration repository with open-sourced noise introduction script We are open! Please give any suggestion and contribute to our effort! GitHub Link: https://github.com/ieee-ceda-datc 21

Thank You! GitHub Link: https://github.com/ieee-ceda-datc 22